/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved.
 * Description: RDMA cmdq command format.
 * Create: 2021-12-30
 */

#ifndef ROCE_NPU_CMD_DEFS_H
#define ROCE_NPU_CMD_DEFS_H

#include "roce_npu_cmd_qp_defs.h"
#include "roce_npu_cmd_gid_defs.h"
#include "roce_npu_cmd_cq_defs.h"
#include "roce_npu_cmd_srq_defs.h"

enum CMD_TYPE_BITMASK_E {
    CMD_TYPE_BITMASK_EXT = 0,
    CMD_TYPE_BITMASK_RSVD1,
    CMD_TYPE_BITMASK_RSVD0,
    CMD_TYPE_BITMASK_PLUGIN_RET,
    CMD_TYPE_BITMASK_VBS,
    CMD_TYPE_BITMASK_DSW,
    CMD_TYPE_BITMASK_NOFAA,
    CMD_TYPE_BITMASK_PLOG,
    CMD_TYPE_BITMASK_DBG = 8,
    CMD_TYPE_BITMASK_VROCE,
    CMD_TYPE_BITMASK_CCF,
    CMD_TYPE_BITMASK_GID,
    CMD_TYPE_BITMASK_MR,
    CMD_TYPE_BITMASK_SRQ,
    CMD_TYPE_BITMASK_CQ,
    CMD_TYPE_BITMASK_QP = 15
};

#define VERBS_CMD_TYPE_QP_BITMASK (1u << CMD_TYPE_BITMASK_QP)
#define VERBS_CMD_TYPE_CQ_BITMASK (1u << CMD_TYPE_BITMASK_CQ)
#define VERBS_CMD_TYPE_SRQ_BITMASK (1u << CMD_TYPE_BITMASK_SRQ)
#define VERBS_CMD_TYPE_MR_BITMASK (1u << CMD_TYPE_BITMASK_MR)
#define VERBS_CMD_TYPE_GID_BITMASK (1u << CMD_TYPE_BITMASK_GID)
#define VERBS_CMD_TYPE_CCF_BITMASK (1u << CMD_TYPE_BITMASK_CCF)
#define VERBS_CMD_TYPE_VROCE_BITMASK (1u << CMD_TYPE_BITMASK_VROCE)
#define VERBS_CMD_TYPE_DEBUG_BITMASK (1u << CMD_TYPE_BITMASK_DBG)
#define VERBS_CMD_TYPE_PLOG_BITMASK (1u << CMD_TYPE_BITMASK_PLOG)
#define VERBS_CMD_TYPE_NOFAA_BITMASK (1u << CMD_TYPE_BITMASK_NOFAA)
#define VERBS_CMD_TYPE_DSW_BITMASK (1u << CMD_TYPE_BITMASK_DSW)
#define VERBS_CMD_TYPE_VBS_BITMASK (1u << CMD_TYPE_BITMASK_VBS)
#define VERBS_CMD_TYPE_EXT_BITMASK (1u << CMD_TYPE_BITMASK_EXT)

enum roce3_cmd_ret_status {
    ROCE_CMD_RET_SUCCESS = 0x0,

    ROCE_CMD_RET_FLR_ERR = 0x1,
    ROCE_CMD_RET_FUNC_INVLD,
    ROCE_CMD_RET_CMDMISC_UNSUPPORT,
    ROCE_CMD_RET_CMDTYPE_UNSUPPORT,
    ROCE_CMD_RET_RET_ADDR_INVLD,
    ROCE_CMD_RET_INDEX_INVLD,
    ROCE_CMD_RET_LOCAL_UNSUPPORT,
    ROCE_CMD_RET_QPC_RSP_ERR = 0x10,
    ROCE_CMD_RET_QPC_STATE_UNEXPECT,
    ROCE_CMD_RET_MODIFY_QP_OPT_ERR,
    ROCE_CMD_RET_MODIFY_QP_EXTEND_OP_API_ERR,
    ROCE_CMD_RET_SQD_QP_FETCH_WQE_ERR,
    ROCE_CMD_RET_RDMARC_SYNC_EXTEND_OP_API_ERR,
    ROCE_CMD_RET_MODIFY_QP_OQID_ERR,
    ROCE_CMD_RET_CQC_STATE_UNEXPECT = 0x18,
    ROCE_CMD_RET_CQC_MISC_API_ERR,
    ROCE_CMD_RET_CQC_CREATE_CACHE_OUT_ERR,
    ROCE_CMD_RET_CQ_RESIZE_API_ERR,
    ROCE_CMD_RET_CQ_EXTEND_OP_API_ERR,
    ROCE_CMD_RET_CQ_TIMER_DEL_ERR,
    ROCE_CMD_RET_CQ_TIMER_REM_ERR,
    ROCE_CMD_RET_SRQC_STATE_UNEXPECT = 0x20,
    ROCE_CMD_RET_SRQ_ARM_SRQ_CONT_EN_ERR,
    ROCE_CMD_RET_SRQ_ARM_SRQ_API_ERR,
    ROCE_CMD_RET_SRQ_EXTEND_OP_API_ERR,
    ROCE_CMD_RET_MR_STATE_ERR = 0x28,
    ROCE_CMD_RET_MR_BIND_MW_API_ERR,
    ROCE_CMD_RET_MR_EXTEND_OP_API_ERR,
    ROCE_CMD_RET_MR_MISC_LOAD_API_ERR,
    ROCE_CMD_RET_MR_MPTC_SYNC_ERR,
    ROCE_CMD_RET_MR_MISC_STORE_API_ERR,
    ROCE_CMD_RET_MR_CACHE_OUT_MPT_ERR,
    ROCE_CMD_RET_MR_CACHE_OUT_MTT_ERR,
    ROCE_CMD_RET_DBG_EXTEND_OP_API_ERR = 0x30,
    ROCE_CMD_RET_DBG_WQE_UPDATE_PI_ERR,
    ROCE_CMD_RET_QU_FLUSH_API_ERR,
    ROCE_CMD_RET_CC_HASH_API_ERR,
    ROCE_CMD_RET_CMD_OP_LB_ERR,
    ROCE_CMD_RET_CMD_OP_SRQN_ERR,
    ROCE_CMD_RET_DIF_TASKID_ALLOC_ERR,
    ROCE_CMD_RET_QP_EXTEND_OP_ERR,
    ROCE_CMD_RET_LOAD_ERR,
    ROCE_CMD_RET_STORE_ERR,
    ROCE_CMD_RET_LOAD_HOST_GPA_ERR,
    ROCE_CMD_RET_CACHE_OUT_ERR,
    ROCE_CMD_RET_CACHE_OUT_MTT_ERR,
    ROCE_CMD_RET_BANK_GPA_FLUSH_ERR,
    ROCE_CMD_RET_INVALID_PARAM_ERR,
    ROCE_CMD_RET_RSVD_ERR = 0xff,
};

enum roce3_cmd_ret_extend_op_err {
    ROCE_CMD_RET_EXTEND_OP_NONE = 0x0,

    ROCE_CMD_RET_EXTEND_OP_RCC_RRE = 0x1,
    ROCE_CMD_RET_EXTEND_OP_RCC_RAE,
    ROCE_CMD_RET_EXTEND_OP_RRWC_RWE,
    ROCE_CMD_RET_EXTEND_OP_RRWC_STA,
    ROCE_CMD_RET_EXTEND_OP_RCC_STA,
    ROCE_CMD_RET_EXTEND_OP_SQC_STA,
    ROCE_CMD_RET_EXTEND_OP_SQAC_STA,
    ROCE_CMD_RET_EXTEND_OP_RQC_STA,
    ROCE_CMD_RET_EXTEND_OP_CQC_TIMEOUT = 0x10,
    ROCE_CMD_RET_EXTEND_OP_CQC_STA,
    ROCE_CMD_RET_EXTEND_OP_SRQC_STA = 0x18,
    ROCE_CMD_RET_EXTEND_OP_MPT_STA = 0x20,
    ROCE_CMD_RET_EXTEND_OP_QPC_DBG_EDIT = 0x28,
    ROCE_CMD_RET_EXTEND_OP_CQC_SRQC_DBG_EDIT
};

/* Mask description of *********ROCE verbs modify qp ******* */
/* ******************************************************************
                                opt   INIT2INIT  INIT2RTR  RTR2RTS  RTS2RTS  SQERR2RTS  SQD2SQD  SQD2RTS
QP_OPTPAR_ALT_ADDR_PATH         0                √           √       √                    √       √
QP_OPTPAR_RRE                   1     √          √           √       √       √            √       √
QP_OPTPAR_RAE                   2     √          √           √       √       √            √       √
QP_OPTPAR_RWE                   3     √          √           √       √       √            √       √
QP_OPTPAR_PKEY_INDEX            4
QP_OPTPAR_Q_KEY                 5     √          √           √       √       √            √       √
QP_OPTPAR_RNR_TIMEOUT           6                √           √       √                    √       √
QP_OPTPAR_PRIMARY_ADDR_PATH     7                √                                        √
QP_OPTPAR_SRA_MAX               8                            √                            √
QP_OPTPAR_RRA_MAX               9                √                                        √
QP_OPTPAR_PM_STATE              10                           √       √                    √       √
QP_OPTPAR_RETRY_COUNT           11                           √                            √
QP_OPTPAR_RNR_RETRY             12                           √                            √
QP_OPTPAR_ACK_TIMEOUT           13                           √                            √
QP_OPTPAR_SCHED_QUEUE           14
QP_OPTPAR_COUNTER_INDEX         15
******************************************************************** */
enum QP_OPTPAR_E {
    QP_OPTPAR_ALT_ADDR_PATH = 0,
    QP_OPTPAR_RRE,
    QP_OPTPAR_RAE,
    QP_OPTPAR_RWE,
    QP_OPTPAR_PKEY_INDEX,
    QP_OPTPAR_Q_KEY,
    QP_OPTPAR_RNR_TIMEOUT,
    QP_OPTPAR_PRIMARY_ADDR_PATH,
    QP_OPTPAR_SRA_MAX = 8,
    QP_OPTPAR_RRA_MAX,
    QP_OPTPAR_PM_STATE,
    QP_OPTPAR_RETRY_COUNT,
    QP_OPTPAR_RNR_RETRY,
    QP_OPTPAR_ACK_TIMEOUT,
    QP_OPTPAR_SCHED_QUEUE,
    QP_OPTPAR_COUNTER_INDEX = 15
};

#define ROCE_QP_ALT_ADDR_PATH_OPT (1u << QP_OPTPAR_ALT_ADDR_PATH)
#define ROCE_QP_RRE_OPT (1u << QP_OPTPAR_RRE)
#define ROCE_QP_RAE_OPT (1u << QP_OPTPAR_RAE)
#define ROCE_QP_RWE_OPT (1u << QP_OPTPAR_RWE)
#define ROCE_QP_PKEY_INDEX_OPT (1u << QP_OPTPAR_PKEY_INDEX)
#define ROCE_QP_Q_KEY_OPT (1u << QP_OPTPAR_Q_KEY)
#define ROCE_QP_RNR_TIMEOUT_OPT (1u << QP_OPTPAR_RNR_TIMEOUT)
#define ROCE_QP_PRIMARY_ADDR_PATH_OPT (1u << QP_OPTPAR_PRIMARY_ADDR_PATH)
#define ROCE_QP_SRA_MAX_OPT (1u << QP_OPTPAR_SRA_MAX)
#define ROCE_QP_RRA_MAX_OPT (1u << QP_OPTPAR_RRA_MAX)
#define ROCE_QP_PM_STATE_OPT (1u << QP_OPTPAR_PM_STATE)
#define ROCE_QP_RETRY_COUNT_OPT (1u << QP_OPTPAR_RETRY_COUNT)
#define ROCE_QP_RNR_RETRY_OPT (1u << QP_OPTPAR_RNR_RETRY)
#define ROCE_QP_ACK_TIMEOUT_OPT (1u << QP_OPTPAR_ACK_TIMEOUT)
#define ROCE_QP_SCHED_QUEUE_OPT (1u << QP_OPTPAR_SCHED_QUEUE)
#define ROCE_QP_COUNTER_INDEX_OPT (1u << QP_OPTPAR_COUNTER_INDEX)

#define ROCE_MODIFY_QP_INIT2INIT_OPT (~0x402e)
#define ROCE_MODIFY_QP_INIT2RTR_OPT (~0x2ee)
#define ROCE_MODIFY_QP_RTR2RTS_OPT (~0x3d6e)
#define ROCE_MODIFY_QP_RTS2RTS_OPT (~0x46e)
#define ROCE_MODIFY_QP_SQERR2RTS_OPT (~0x2e)
#define ROCE_MODIFY_QP_SQD2SQD_OPT (~0x7fee)
#define ROCE_MODIFY_QP_SQD2RTS_OPT (~0x46e)
#define ROCE_MODIFY_QP_RTS2RTS_EXP_OPT (~0x10000)
#define ROCE_MODIFY_QP_RTS2SQD_SQD_EVENT_OPT (0x80000000)

/* ********************************************************************************** */
#pragma pack(4)
typedef struct tag_roce_verbs_cmd_header {
    union {
        u32 value;

        struct {
            u32 version : 8;
            u32 rsvd : 8;
            u32 cmd_bitmask : 16; // CMD_TYPE_BITMASK_E
        } bs;
    } dw0;

    u32 index; // qpn/cqn/srqn/mpt_index/gid idx

    u32 opt; //

    union {
        u32 value;

        struct {
            u32 cmd_type : 8;
            u32 rsvd : 7;
            u32 seg_ext : 1;
            u32 cmd_len : 16; // verbs cmd total len(include cmd_com),unit:byte
        } bs;
    } dw3;
} roce_verbs_cmd_header_s;
#pragma pack()

typedef struct tag_roce_uni_cmd_gid {
    roce_verbs_cmd_header_s com;
    roce_verbs_gid_attr_s gid_attr;
} roce_uni_cmd_update_gid_s;

typedef struct tag_roce_uni_cmd_clear_gid {
    roce_verbs_cmd_header_s com;
    roce_verbs_clear_gid_info_s gid_clear;
} roce_uni_cmd_clear_gid_s;

typedef struct tag_roce_uni_cmd_qurey_gid {
    roce_verbs_cmd_header_s com;
} roce_uni_cmd_query_gid_s;

typedef struct tag_roce_uni_cmd_flush_mpt {
    roce_verbs_cmd_header_s com;
} roce_uni_cmd_flush_mpt_s;

typedef struct tag_roce_uni_cmd_mpt_query {
    roce_verbs_cmd_header_s com;
} roce_uni_cmd_mpt_query_s;

typedef struct tag_roce_uni_cmd_sw2hw_mpt {
    roce_verbs_cmd_header_s com;
    roce_verbs_mr_attr_s mr_attr; /* When creating a MR/MW, you need to enter the content of the MPT Context. */
} roce_uni_cmd_mpt_sw2hw_s;

typedef struct tag_roce_uni_cmd_modify_mpt {
    roce_verbs_cmd_header_s com;
    roce_verbs_mr_sge_s mr_sge;
} roce_uni_cmd_modify_mpt_s;

typedef struct tag_roce_uni_cmd_mpt_hw2sw {
    roce_verbs_cmd_header_s com;
    roce_verbs_mtt_cacheout_info_s dmtt_cache;
} roce_uni_cmd_mpt_hw2sw_s;

typedef struct tag_roce_uni_cmd_query_mtt {
    roce_verbs_cmd_header_s com;
    roce_verbs_query_mtt_info_s mtt_query;
} roce_uni_cmd_query_mtt_s;

typedef struct tag_roce_uni_cmd_creat_cq {
    roce_verbs_cmd_header_s com;
    roce_verbs_cq_attr_s cq_attr;
} roce_uni_cmd_create_cq_s;

typedef struct tag_roce_uni_cmd_resize_cq {
    roce_verbs_cmd_header_s com;
    roce_verbs_cq_resize_info_s cq_resize;
} roce_uni_cmd_resize_cq_s;

typedef struct tag_roce_uni_cmd_modify_cq {
    roce_verbs_cmd_header_s com;
    roce_verbs_modify_cq_info_s cq_modify;
} roce_uni_cmd_modify_cq_s;

typedef struct tag_roce_uni_cmd_cq_hw2sw {
    roce_verbs_cmd_header_s com;
    roce_verbs_mtt_cacheout_info_s cmtt_cache;
} roce_uni_cmd_cq_hw2sw_s;

typedef struct tag_roce_uni_cmd_roce_cq_query {
    roce_verbs_cmd_header_s com;
} roce_uni_cmd_cq_query_s;

typedef struct tag_roce_uni_cmd_creat_srq {
    roce_verbs_cmd_header_s com;
    roce_verbs_srq_attr_s srq_attr;
} roce_uni_cmd_create_srq_s;

typedef struct tag_roce_uni_cmd_srq_arm {
    roce_verbs_cmd_header_s com;
    roce_verbs_arm_srq_info_u srq_arm;
} roce_uni_cmd_srq_arm_s;

typedef struct tag_roce_uni_cmd_srq_hw2sw {
    roce_verbs_cmd_header_s com;
    roce_verbs_srq_hw2sw_info_s srq_cache;
} roce_uni_cmd_srq_hw2sw_s;

typedef struct tag_roce_uni_cmd_srq_query {
    roce_verbs_cmd_header_s com;
} roce_uni_cmd_srq_query_s;

typedef struct tag_roce_uni_cmd_modify_qpc {
    roce_verbs_cmd_header_s com;
    roce_verbs_qp_attr_s qp_attr;
} roce_uni_cmd_modify_qpc_s;

typedef struct tag_roce_uni_cmd_qp_modify2rst {
    roce_verbs_cmd_header_s com;
} roce_uni_cmd_qp_modify2rst_s;

typedef struct tag_roce_uni_cmd_qp_modify_rts2sqd {
    roce_verbs_cmd_header_s com;
    u32 sqd_event_en;
} roce_uni_cmd_qp_modify_rts2sqd_s;

typedef struct tag_roce_uni_cmd_qp_query {
    roce_verbs_cmd_header_s com;
} roce_uni_cmd_qp_query_s;

typedef struct tag_roce_uni_cmd_qp_cache_invalid {
    roce_verbs_cmd_header_s com;
    roce_verbs_qp_hw2sw_info_s qp_cache;
} roce_uni_cmd_qp_cache_invalid_s;

typedef struct tag_roce_uni_cmd_cq_cache_invalid {
    roce_verbs_cmd_header_s com;
    roce_verbs_xq_mtt_info_s mtt_info;
} roce_uni_cmd_cq_cache_invalid_s;

typedef struct tag_roce_uni_cmd_modify_ctx {
    roce_verbs_cmd_header_s com;
    roce_verbs_modify_ctx_info_s ctx_modify;
} roce_uni_cmd_modify_ctx_s;

typedef struct tag_roce_uni_cmd_cap_pkt {
    roce_verbs_cmd_header_s com;
} roce_uni_cmd_cap_pkt_s;


#endif /* ROCE_NPU_CMD_DEFS_H */
